SLIM-ADC-12
Analog to Digital Converter
Updated 4-30-08.  Update page for name changes.  No pwb or schematic changes.
Updated 7-14-08.  Parts list revised for incorrect switch (SW1, SW2) part number.

SLIM-ADC-12, AtoD Converter, 12 bit, size A
Use your mouse's "right click" and "Save Link" to download:
a.  SKSLIM-ADC-12, Schematic, in ExpressPCB software.
b. PWB-ADC8, Base artwork for PWB, in ExpressPCB software.  Use this drawing to order the pwb from Express, or to locate the parts on the SLIM-ADC-12.
c. PLSLIM-ADC-12 rev A, Parts List in text format.  Open with Exel or Lotus, etc.

    The SLIM-ADC-12 is a dual 12 bit converter using the less expensive LTC1860.  The U2 AtoD will convert the J1 input of 0 to 2.8 volts for a maximum of 4096 bits.  This equates to 684 uv per bit.  The voltage divider R2 and R3 determine the reference of the AtoD and can be modified to any value between 1.5 volts and 5.0 volts.  This design sets it to 2.8 volts.
    The U3 AtoD will convert the J2 input of 1.0 volts to 4.0 volts for a maximum of 4096 bits.  This equates to 732 uv per bit.  The voltage divider R5, R6, and R7 determine the reference and minimum input of the AtoD.   This voltage divider could also be modified for specialized inputs.
    Both A/D's will capture, and clock out their data concurrently.  The software commands both U2 and U3 to begin conversion with a single toggle of the signal, "CONVERT".  12 toggles of the signal, "SERCLOCK", causes the I.C. to output a serial stream of 12 bits.  The SDO outputs of the AtoD I.C.'s have limited current capability.  Therefore, Q1 and Q2 provide current sinking to drive the "WAIT" and "ACK" lines on the LPT port of the Computer.  The Computer's LPT port is nominally a TTL compatable input with a pull up resistor to +5 volts.
    The circuit is designed with thru hole pads, to allow each input to be connected to an external switch. The switch selects the amount of capacitance to be placed in shunt with the input.  Each switch is a single pole, dual throw, with a non-connecting center position.   This allows a selection of 3 different integration times (Video Bandwidth).  This module is expected to be mounted very close to the front panel of the integrated system so that the user can mount the switches on the front panel and maintain very short leads from the switches to the bottom of the module.
    The base PWB has the part number, PWB-ADC8.  The "8" signifies the use of an 8 pin SOIC package.  There are other A/D I.C.s with this package.  More A/D SLIMs could be created from this design.
SKSLIM-ADC-12, Schematic of SLIM-ADC-12
slim/skslim_adc_12.gif

PWB-ADC8, Artwork for pwb, and Layout for SLIM-ADC-12
slim/pwb_adc_8.gif

How to Control the SLIM-ADC-12
    Two lines control this module, the CONVERT and SERCLOCK.  Both AtoD chips are controlled together.  During the Acquision time, these lines are low.  The in-chip sample and hold circuits, are in the "sample" mode.  To begin Conversion, the CONVERT is commanded high, then commanded low.  This initiates the in-chip sample and hold circuits, to the "hold" mode.  Any voltage changes on the inputs will be disregarded.  It now takes approximately 3 usec for the 12 bit conversion to take place.  When complete, the MSB of the 12 bit data word will be present on the SDO pin, it's inversion on the line back to the computer (WAIT or ACK).  Each time the SERCLOCK is brought high, then low, the data word is shifted by one bit.  It takes 12 SERCLOCK's to shift out the 12 bit data word.
  The computer action should look like this:
CONVERT and SERCLOCK: low.
CONVERT to high.  Initiates the A to D conversion process.
CONVERT to low, then wait at least 3 usec.
SERCLOCK to high.  D11 MSB is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D10 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D9 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D8 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D7 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D6 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D5 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D4 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D3 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D2 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D1 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit is shifted.
SERCLOCK to high.  D0 bit is valid on SDO, and can be read by computer
SERCLOCK to low.  Next data word bit on SDO, is an invalid zero.